On-chip stochastic communication [SoC applications]
| Title | On-chip stochastic communication [SoC applications] |
| Publication Type | Conference Papers |
| Year of Publication | 2003 |
| Authors | Dumitras T, Marculescu R. |
| Conference Name | Design, Automation and Test in Europe Conference and Exhibition, 2003 |
| Date Published | 2003/// |
| Keywords | buffer overflow, CMOS technology, CMOS technology scaling, Costs, data upsets, Design automation, Digital audio players, Fault tolerance, Fault tolerant systems, generic tile-based architecture, integrated circuit design, integrated circuit interconnections, interconnect correctness requirements, Logic Design, logic simulation, MP3 encoder, Multiprocessor interconnection networks, on-chip fault-tolerance, on-chip stochastic communication, packet drops, Pervasive computing, Robustness, SoC design, SoC verification, Stochastic processes, Synchronisation, synchronization failures, system latency, system-level fault-tolerance, system-on-chip, systems-on-chip, video coding |
| Abstract | As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for systems-on-chip (SoCs) are rapidly increasing due to the inefficiency of traditional CAD tools. Relaxing the requirement of 100% correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires that SoCs be designed with some system-level fault-tolerance. In this paper, we introduce a new communication paradigm for SoCs, namely stochastic communication. The newly proposed scheme not only separates communication from computation, but also provides the required built-in fault-tolerance to DSM failures, is scalable and cheap to implement. For a generic tile-based architecture, we show how a ubiquitous multimedia application (an MP3 encoder) can be implemented using stochastic communication in an efficient and robust manner. More precisely, up to 70% data upsets, 80% packet drops because of buffer overflow, and severe levels of synchronization failures can be tolerated while maintaining a low latency. |